1. Field of the Invention
The present invention relates to a channel equalizer for a digital television, and more particularly, to a partial fractionally spaced channel equalizer for a digital television which is capable of removing long and short ghosts.
2. Description of the Background Art
Generally, a channel equalizer compensates or equalizes a distortion generated when transmission signals pass multiple paths in a digital transmission system such as a high definition picture television. That is, the channel equalizer removed an interference noise generated in a digital television when a transmission channel is defective appears as a ghost phenomenon that images are overlapped on the digital TV screen.
FIG. 1 is a schematic block diagram of a tap spaced decision feedback equalizer (TS-DFE) in accordance with a conventional art.
As shown in the drawing, the TS-DFE includes feedforward filter unit 101 for receiving a sampling input signal (Si) of 10.76 MHz, a feedback filter unit 102 for receiving sliced output signals of a slicer which will be explained later, an adder 19 for adding tap signals outputted from the feedforward filter unit 101 and the feedback filter unit 102 and generating an equalizer output signal (Xi), a slicer 22 for receiving the equalizer output signal (Xi) and outputting a decision data (Di), a subtractor 21 for subtracting the equalizer output signal (Xi) from the decision data (Di) and outputting an error signal (Ei), and a multiplier 20 for multiplying the error signal (Ei) and a step size (s) to generate a step error signal (sEi) and outputting the step error signal (sEi) to the feedforward filter unit 101 and the feedback filter unit 102.
The feedforward filter unit 101 includes a first delay array unit 11 having a plurality of delays (Zxe2x88x921) for receiving and sequentially delaying the input signal (Si) sampled at a sampling speed of 10.76 Mz, a first multiplying unit 12 having multipliers for respectively multiplying the delay signals (Si-1, Si-2, . . . Si-6) outputted from the plurality of delays (Zxe2x88x921) and the previous error signals (sEi-1), a first adding unit 13 for accumulating the multiplying result of each multiplier in the first multiplying unit 12 and outputting coefficients (C0, C1, C2, . . . C6), and a second multiplying unit 14 having a plurality of multipliers for respectively multiplying coefficients (C0, C1, C2, . . . , C6) and the input signal (Si) and outputting feedforward filter tap signals.
Like the feedforward filter unit 101, the feedback filter unit 102 includes a second delay array unit 15 having a plurality of delays (Zxe2x88x921) for receiving the decision data (Di) from the slicer 22, sequentially delaying them, and outputting delay signals (Di-1, Di-2), a third multiplying unit 16 having multipliers for respectively multiplying the delay signals ((Di-1, Di-2) and the previous error signals (sEi-1), a second adding unit 17 for accumulating the multiplying result of each multiplier in the third multiplying unit 17 and outputting coefficients (C7 and C8), and a fourth multiplying unit 18 having a plurality of multipliers for respectively multiplying the coefficients (C7, C8) and the delay signals (Di-1, Di-2) and outputting feedback filter tap signals.
The operation of the conventional tap spaced decision feedback equalizer (TS-DFE) as described above will now be explained.
First, when the sampled input signal (Si) is inputted to the first delay array unit 11 of the feedforward filter unit 101, the delays in the first delay array unit 11 as many as taps respectively delay the input signal and generate delay signals (Si-1, Si-2, . . . , Si-6). Each delayed signal (Si-1, Si-2, . . . Si-6) and the input signal (Si) are outputted to the first and the second multiplying units 12 and 14.
At this time, the second multiplying unit 14 multiplies the input signal (Si) and the delayed signals (Si-1, Si-2, . . . Si-6) and the coefficients (C0, C1, . . . , C6) outputted from the first adding unit 13 to generate the feedforward filter tap signals, and outputs the feedforward filter tap signals to the adder 19. Then, the adder 19 adds the feedforward filter tap signals to generate an equalizer output signal (Xi) and outputs the equalizer output signal (Xi) to the subtractor 21 and the slicer 22.
Upon receipt of the equalizer output signal (Xi), the slicer 22 generates a decision data (Di) by using the equalizer output signal (Xi) and outputs it to the subtractor 21 and the second delay array unit 15 of the feedback filter unit 102.
The subtractor 21 subtracts the decision data (Di) from the equalizer output signal (Xi) and generates the error signal (Ei) and outputs it to the multiplier 20. Then, the multiplier 20 multipliers the error signal (Ei) by a predetermined step size (S) to generate a step error signal (sEi), and outputs the step error signal (sEi) to the first multiplying unit 12 of the feedforward filter unit 101 and the third multiplying unit 16 of the feedback filter unit 102.
Like the operation of the feedforward filter unit 101, the second delay array unit 15 of the feedback filter unit 102 receives the decision data (Di) from the slicer 22, sequentially delays it to generate delayed signals (Di-1, Di-2), and outputs them to the third and the fourth multiplying units 16 and 18. Then, the third multiplying unit 16 multiplies each delayed signal (Di-1, Di-2) and the previous error signals (sEi-1) outputted from the multiplier 20, and outputs the multiplying result to the second adding unit 17.
The second adding unit 17 accumulates the multiplying result to generate coefficients (C7, C8) and outputs them to the fourth multiplying unit 18.
The fourth multiplying unit 18 multiplies the delayed signals (Di-1, Di-2) by the coefficients (C7, C8) to generate feedback filter tap signals, and outputs the feedback filter tap signals to the adder 19, so that the feedback filter unit 102 is cooperatively operated with the feedforward filter unit 101.
Accordingly, the TS-DFE of the conventional art equalizes the 10.76 MHz input signal by using the seven taps of the feedforward filter unit 101 and the two taps of the feedback filter unit 102 which receive and sequentially delay the input signal (Si). That is, the TS-DFE updates the coefficients and the operation of which will be explained as below in detail.
The function of the first and the second adding units 13 and 17 is expressed by the following equation (1).
C(n+1)=C(n)+sxc2x7Ei(n)xc2x7Xi(n)xe2x80x83xe2x80x83(1) 
Where C(n) and C(n+1) denotes coefficients at a symbol time (n) and a symbol time (n+1), ""s"" denotes a step size, Ei(n) denotes an error signal outputted from the subtractor 21 at a symbol time xe2x80x98nxe2x80x99, and Xi(n) denotes an equalizer output signal outputted from the adder 19 at the symbol time xe2x80x98nxe2x80x99. That is, the coefficient at the symbol time (n+1) can be expressed by the addition of the coefficient of the previous symbol time (n) and the value obtained by multiplying the equalizer output signal by the error signal having a predetermined step.
FIG. 2 is tap positions on a time axis of the TS-DFE of FIG. 1, which show a removable preghost and postghost range referenced to a main tap. That is, the TS-DFE of FIG. 1 with 9 taps removes ghosts a from xe2x88x923 T to 5 T Here, T is symbol time ({fraction (1/10.76)} MHz).
Accordingly, as for the TS-DFE of the conventional art, if the number of the taps is a lot in the filter unit, the distortion of a channel caused due to the long ghost at an external environment can be properly compensated, so that an interference between symbols can be easily removed.
However, with the conventional TS-DFE, a short ghost between symbols, for example, a reflection near the receiver by persons"" motion, can not be removed. In addition, in case that a symbol time restoring circuit is not perfectly operated, the performance of the equalizer is possibly degraded due to the symbol time noise.
In an effort to solve the problem, there has been proposed an N times fractionally spaced channel equalizer as shown in FIG. 3 in which an input signal over-sampled by N times (N greater than =2) the above mentioned sampled input signal is received and N number of taps exist at one symbol position, thereby removing an echo signal generated within a very short time, while not much degrading its performance.
FIG. 3 is a schematic block diagram of a T/2 or half tap spaced decision feedback equalizer (T/2 TS-DFE) in accordance with a conventional art.
As shown in the drawing, the T/2 TS-DFE includes a feedforward filter unit 101 for receiving a sampling input signal (Si) of 21.52 MHz, a feedback filter unit 102 for receiving sliced output signals of a slicer which will be explained later, a first adder 31 for adding tap signals outputted from the feedforward filter unit 101, decimator 32 for down-sampling the addition results outputted from the first adder 31 for a predetermined time, a third adder 34 for adding tap signals outputted from the feedback filter unit 102, a second adder 33 for adding the output signal of the decimator 32 and the output signal of the third adder 34 and generating an equalizer output signal (Xi), a slicer 37 for receiving the equalizer output signal (Xi) and outputting a decision data (Di), a subtractor 36 for subtracting the equalizer output signal (Xi) from the decision data (Di) and outputting an error signal (Ei), and a multiplier 35 for multiplying the error signal (Ei) and a predetermined step size (s) to generate a step error signal (sEi), and outputting the step error signal (sEi) to the feedforward filter unit 101 and the feedback filter unit 102.
In this respect, the feedforward filter unit 101 and the feedback filter unit 102 are the same as those of the TS-DFE of FIG. 1.
The operation of the conventional T/2 TS-DFE constructed as described above will now be explained.
When the input signal (Si) having a 21.52 MHz sampling symbol rate is inputted to the first delay array unit 11 of the feedforward filter unit 101, delays (Zxe2x88x921) as many as the taps included in the first delay arraying unit 11 respectively delay the input signal Si to generate delayed signals (Si-1, Si-2, . . . , Si-6), and outputs the delayed signals (Si-1, Si-2, . . . , Si-6) and the input signal (Si) to the first and the second multiplying units 12 and 14.
At this time, the adders included in the first adding unit 13 respectively accumulate the signals outputted from the first multiplier 12 and generates coefficients (C0, C1, . . . , C6).
Then, the second multiplying unit 14 multiplies the input signal (Si) and the delayed signals (Si-1, Si-2, . . . , Si-6) by the coefficients (C0, C1, . . . , C6) outputted from the first adding unit 13 to generate feedforward filter tap signals and outputs them to the first adder 31, the first adder 31 adds the feedforward filter tap signals and outputs them to the decimator 32.
Upon receipt of the added feedforward filter tap signals, the decimator 32 samples and outputs a signal corresponding to the symbol time. Then, the second adder 33 adds the sampled signal outputted from the decimator 32 and the signal outputted from the third adder 34 to generates an equalizer output signal (Xi), and outputs the equalize output signal to the slicer 37 and the subtractor 36.
Upon receipt of the equalizer output signal (Xi), the slicer 37 generates a decision data (Di) by using the equalization signal (Xi) and outputs the decision data (Di) to the subtractor 36 and the second delay array unit 15 of the feedback filter unit 102.
At this time, when the subtractor 36 subtracts the equalizer output signal (Xi) from the decision data (Di) to generate an error signal (Ei) and outputs the error signal (Ei) to the multiplier 35, the multiplier 35 multiplies the error signal (Ei) by the step size (s) predetermined by a user to generate a step error signal (sEi), and outputs the step error signal (sEi) to the first multiplying unit 12 of the feedforward filter unit 101 and the third multiplying unit 16 of the feedback filter unit 102.
Meanwhile, like the operation of the feedforward filter unit 101, the second delay array unit 15 of the feedback filter unit 102 receives the decision data (Di) from the slicer 37, sequentially delays it to generate delayed signals (Di-1, Di-2), and outputs them to the third and the fourth multiplying units 16 and 18.
Then, the third multiplying unit 16 multiplies the delayed signals (Di-1, Di-2) by the previous error signals outputted from the multiplier 20 and outputs the multiplication result to the second adding unit 17.
The second adding unit 17 accumulates the multiplication result, generates coefficients (C7, C8) and outputs them to the fourth multiplying unit 18.
The fourth multiplying unit 18 multiplies the delayed signals (Di-1, Di-2) by the coefficient (C7, C8) to generate feedback filter tap signals and outputs the feedback filter tap signals to the third adder 34.
Then, the third adder 34 adds the feedback filter tap signals and outputs the addition result to the second adder 33, so that the feedback filter unit 102 is cooperatively operated with the feedforward filter unit 101.
FIG. 4 is tap positions on a time axis of the T/2 TS-DFE of FIG. 3, which show a removable preghost and postghost range referenced to a main tap. That is, the T/2 TS-DFE of FIG. 3 with 9 taps removes ghosts a from xe2x88x921.5 T to 3 T Here, T is symbol time ({fraction (1/10.76)} MHz). In other words, as shown in FIG. 4, with the T/2 TS-DFE, seven taps are arranged between xe2x88x921.5 T and 1.5 T centering the main tap (0) of the feedforward filter unit 101, and two taps are arranged between 2 T ad 3 T of the feedback filter unit 102, to thereby remove an echo signal between xe2x88x921.5 T and 3 T.
However, in case of the conventional TS-DFE of FIG. 1, though it is favorable in that the ghost signal can be removed in the wide frequency range, that is, for example, between xe2x88x923 T and 3 T by the feedforward filter unit consisting of seven taps, it has a problem that ghost between taps or symbols can not be removed.
Meanwhile, in case of the conventional T/2 TS-DFE of FIG. 3, the taps are arranged with its space reduced by half (for example, seven taps are arranged between the frequency range from xe2x88x921.5 T to 1.5 T), thereby reducing the ghost between taps or symbols. However, in order to the ghost in the same range as the ghost range removed by the TS-DFE of FIG. 1, double the number of taps of TS-DFE of FIG. 1 are to be included. Thus, the T/2 TS-DFE of FIG. 3 has problems that the circuit size is enlarged, its hardware becomes complicated and the TS-DFE is not operated at a high speed.
Therefore, an object of the present invention is to provide a partial fractionally spaced equalizer for a digital television which is capable of removing both long and short ghosts by adjusting the number of taps in a filter, and of operating at a high speed with its circuit size reduced.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a partial fractionally spaced equalizer for a digital television comprising, a feedforward filter unit for receiving an input signal sampled at a predetermined frequency, which is divided a first region having a symbol spaced tap and a second region having fractional spaced taps narrower than the symbol spaced tap, a feedback filter unit having symbol spaced taps, a equalizer signal generator for processing feedforward tap signals outputted from the feedforward filter unit and the feedback tap signals outputted from the feedback filter unit and generating equalizer signals, a slicer for slicing the equalizer signals to generate a decision data and outputting the decision data to the feedback filter unit, and an error generator for generating a compensating error signal by subtracting the equalizer signal from the decision data.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.